Semiconductor manufacturing, from early manufacturing up to the present VLSI and ULSI integrated circuits, has been largely driven by the need to increase the speed and density of the device formed thereon. This is typically accomplished by implementing more aggressive design rules to allow smaller transistors to be formed. As transistor sizes shrink, the area to form conductive interconnect layers is reduced, and more aggressive processes are required to minimize the dimensions of interconnect layers formed, or more interconnect layers need to be formed to perform the necessary routing. Additionally, these interconnects must accommodate the power distribution and power dissipation requirements of more and smaller transistors.
It is well known that a single defect in a metal interconnect layer can render a device useless. Unfortunately, these metal interconnect defects are discovered only after the costly steps of forming the active transistor devices. For this reason a method of forming a finished semiconductor device that reduces the number of device defects caused by the metal layers of a semiconductor device would be useful.